Panasonic Corporation announced that it has developed a sheet-form encapsulation material (CV2008 series) for coreless package substrates that enables thinner-profile and lower-cost semiconductor packages.

The sheet-form encapsulation material, scheduled for mass production from June 2016, is optimized for the insulation layers of coreless package substrates.

Its suitability for large-area encapsulation allows thinner packages to be manufactured at lower cost.

This new product has the following features:

1. A sheet-form encapsulation material with a uniformly produced insulation layer thickness is ideal for the new coreless process*1, as it eliminates the need for laser drilling processing. The insulation layer for a package substrate can be produced using a large-area press process, enabling the mass production of packages at lower cost.
   – Sheet thickness is available in the range of 20 – 200 µm.
2. The high rigidity of the thin sheet encapsulation material minimizes any warpage of packages and contributes to a thinner profile. Modulus of elasticity: 17000 MPa at 25°C.
3. A low shrinkage rate of material ensures connection reliability to be maintained during high-temperature reflow processes, increasing the production yield of the package assembly process. – Shrinkage rate: 0.003%*2

*1: Copper pillar resin encapsulation process
*2: Shrinkage rate before and after IR reflow at up to 250°C, 4 passes (JIS-K6911)

Suitable applications:
Copper pillar resin encapsulation type coreless package substrates, etc.

Remarks:
This product was exhibited at ECTC 2016 at The Cosmopolitan of Las Vegas, Nevada, USA, from May 31 to June 3, 2016.